Self-timing encoded tag reader

ABSTRACT

A label is disclosed having an aligner symmetrically disposed relative to a circular pattern of circumferentially arranged photosensible information. Also disclosed is a reader having a probe engageable with the label aligner to properly locate the information pattern relative to a scanning transducer which is radially displaced about the probe for movement in a circular scan path coextensive with the circular information pattern on the label. The reader additionally includes clock signal means which generates clock signals at a rate substantially exceeding the information scanning rate, and sample signal means responsive to the clock signal and to a start mark on the tag for generating clock signals in synchronism with the scanning of the circularly arranged information.

United States Patent 3,474,234 10/1969 R'iegeretal ...250/2l9(lDC)XPrimary Examiner-Maynard R. Wilbur Assistant ExaminerThomas J. SloyanAttorney-Wood, Herron and Evans ABSTRACT: A label is disclosed having analigner symmetrically disposed relative to a circular pattern ofcircumferentially arranged photosensible infonnation. Also disclosed isa reader having a probe engageable with the label aligner to properlylocate the information pattern relative to a scanning transducer whichis radially displaced about the probe for movement in a circular scanpath coextensive with the circular information pattern on the label. Thereader additionally includes clock signal means which generates clocksignals at a rate substantially exceeding the information scanning rate,and sample signal means responsive to the clock signal and to a startmark on the tag for generating clock signals in synchronism with thescanning of the circularly arranged information.

PATENTEUJUNISIQH 3,585,366

POSITION WITHIN CHA ABCD INVIEN'H )R.

START MESSAGE y/ SPACE c005 M W PATENTEUJUNISISH 3,585,366

SHEET 3 [1F 8 POS. DC SOURC DATA START RDY. TO RECE CLOCK INVENTORTPATENTEDJUHISIHR 3,585,366

sum u or 8 TIMING LAMP SCAN LAMP,d SCAN MOTOR TO LAMP (I7) PATENTED JUN]51% SHEET 8 BF 8 WMS WNEN PATENTEI] JUN? 519m SHEET 7 [IF 8 WWWPATENTEI] JUNIBIBYI SHEET 8 OF 8 3,585,366

o mve xwbq oo o 0 mg mwhzaoo ham! mmmJDm x0040 o v SELF-TIMING ENCODEDTAG READER This invention relates to encoded tag reading apparatus andmore particularly to apparatus and more particularly to apparatus forreading merchandise tags having circularly arranged photosensibleinformation imprinted thereon.

Broadly illustrative of the general type of tag suitable for use withthe reader of this invention are the tags disclosed and claimed in thecopending applications of Paul H. Hamisch for Improved Machine ReadableMerchandise Tag," Ser. No. 601,683, filed Dec. 14, 1966 now U.S. Pat.No. 3,409,760, of Herbert LaMers for Interpreting System, Ser. No.260,748, filed Feb. 25, 1963, now U.S. Pat. No. 3,413,447 and of Riegeret al. for Improved Encoded Tag Reader," Ser. No. 672,629, filed, Oct.3, 1967 now U.S. Pat. No. 3,474,234. In each of the above applications atag is shown which embodies a construction fundamentally different fromthat employed in machine readable tags previously known in the art.Specifically, each tag disclosed is predicated on the concept ofproviding a central alignment hole in the tag about which machinereadable information such as encoded price, description, inventorynumber, etc., is imprinted in the form of circularly arranged patternsof equally circumferentially spaced photosensible marks.

The merit of a tag having circumferentially spaced, circularly arrangedencoded information symmetrically disposed relative to an alignment holeis that the need for careful registration between the tag and readerduring reading is virtually nonexistent. To secure alignment between thetag and reader, it is only necessary to insert a suitably positionedprobe, which protrudes from thereader, into the hole in the tag. Thisautomatically aligns tag scanning transducers located in the reader withthe circular rings or patterns of encoded machine readable informationimprinted on the tag. Precise angular orientation of the tag and theprobe is unnecessary. Because of this ease of registration, tags on thistype have come to represent a fundamental advance in the encoded machinereadable tag field.

Readers of the general type to which this invention is directed, andcapable of reading tags of the type disclosed in the above-referencedapplications, can be classified in two categories on the basis of themanner in which timing of the data sensing operation is accomplished.Into the first category fall those readers which require timing data tobe imprinted on the tag along with the information data such as price,etc. These readers, of which the readers disclosed in the LaMers andHamisch applications are illustrative, include timing data sensing meanswhich sense timing data on the tag as the tag is being scanned, therebygenerating timing signals in synchronism with the sensing of informationdata.

Into the second category fall readers which generate timing signalswithout resort to transducing special purpose timing data imprinted onthe tag. Such readers are self-timing" in the sense that they generatetiming signals internally," rather than via timing data on the tag.Readers in the second category, termed self-timing, provide a definiteadvantage in that i the tag which bears the information data to be readcan be smaller in size since no provision must be made for imprintingthe timing data. Smaller tags, obviously, are less expensive. Further,tags without timing data thereon do not require a separate time dataimprinting step, which step also adds to cost.

Illustrative of readers in the second category are the readers disclosedin the Rieger et al. applications and in the copending application ofHumbarger for Improved Self-Timing Encoded Tag Reader/f Ser. No.760,841, filed Sept. 19, 1968. The Reiger et al. readerutilizes aslotted timing disc which initiates rotation via a selectively operableclutch only after the sensing of a start mark on the tab correspondingto the beginning of the message. The slotted timing disc, once rotating,periodically interrupts a light beam to generate timing signals at arate equal to and in synchronism with the sensing of the informationdata positions scanned by a rotating transducer driven in common withthe timing disc. The use of the clutch arrangement in the Rieger et al.reader introduces unnecessary bulk, weight and wear points which tend toreduce compactness and overall reliability.

The Humbarger reader eliminates the need for a clutch by reason of usinga slotted clock or timing disc which can be fixedly secured to thescanning assembly and which is capable of generating clock signals atrates significantly in excess of that provided by the Rieger et al.disc. In accordance with the Humbarger reader, a slotted clock or timingdisc is provided which is fixed to the scanning assembly, and which,from the moment scanning assembly movement begins, generates clocksignals at a rate which exceeds the information data scanning rate by afactor of N. The clock signals are input to a counting means which, inresponse to sensing a start mark on the tag corresponding to thebeginning of the information data, such as price of the like, countsonly the clock signals generated after the start mark is sensed and, asa consequence thereof, generates periodic data sampling signalscoincident with every Nth clock signal counted. Since N clock signalsare generated for every data bit position on the tag, the samplingsignals produced every Nth clock count occur at a rate of one per databit position. Additionally, since the counting of the clock signalsstarts with the sensing of the start mark, which sensing is N clocksignals prior to the first data position by reason of the fixed drivebetween the clock ring and data sensing transducer, the first samplingsignal produced at the 'Nth clock count occurs in synchronism withthescanning of the first data position following the start mark.Likewise, subsequent data 1 sampling signals produced at N clock countintervals occur in synchronism with the sensing of subsequent datapositions.

Thus, regardless of variations in the rotational .speed of the scanningassembly or the initial angular position of the start mark relative tothe data sensing transducer, the sampling signals are always generatedin synchronism with data position sensing.

The reader to which this invention is directed and which is claimedherein falls into the category of self-timed readers, and constitutes animprovement of the reader claimed in the above-noted Humbarger copendingapplication. In the reader claimed in the Humbarger application, norovision is made for altering the location of the sampling signalsrelative to the data positions to accommodate and account for variationsin the width of the machine readable data marks. The disadvantage ofsuch an arrangement is that the sampling signals occur early in thesensing of data marks which are wider than average, and occur late inthe sensing of data marks which are narrower than average. Should theleading edge of a data transducer signal generated by sensing a narrowmark be degraded, for example, be below the threshold value utilized fordiscriminating between logical Is or data marks and logical Os or theabsence of marks, the existence of a sampling signal at an early pointin the data transducer output signal which typifies operation whennarrow marks are present results in a data recognition error. Since thedata signal has a' value below the discriminatory threshold level at thepoint where the sampling signal occurs, the logic circuitry recognizesthe sensed mark as a logical 0 instead of a logical "1.

Accordingly, it ha been an objective of this invention to provide areader which alters the position of the data sampling signal toaccommodate data marks of varying widths, and thereby avoid readingerrors occasioned by failure to discriminatebetween logical l s andlogical 0s" represented respectively by the presence of and absence ofmachinere a da ble marks of above-average or below-average widths. Thisobjective has been accomplished in accordance with the principles ofthis invention by providing, in a reader of the general Humbarger type,(a) means responsive to the clock signals generated during the sensingof a data mark for providing an output correlated to the width of thesensed data mark, and (b) means responsive to said width-correlatedoutput for producing, regardless of the deviation of the width of a markfrom an average or desired value, sampling signals corresponding in timeto the sensing of the approximate midpoint of the data being sensed.

An advantage of a reader of the foregoing type is that tag readingreliability is increased. The reader can interchangeably read withaccuracy and without adjustment tags of one printing batch having narrowwidth data marks and tags of another printing batch haVing wide widthdata marks.

Other objectives and advantages of this invention will be more readilyapparent from a detailed description of the invention taken inconjunction with the accompanying drawings in which:

FIG. I is a perspective view of a preferred embodiment of the tag readerof this-invention, showing its use in connection with reading a tag onan article of merchandise.

FIG. 2 is one form of machine readable tag capable of use with thereader of this invention.

FIG. 3 is a preferred coding chart suitable for use in encoding a tag.

FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 1 showingthe general relationship of the principal components of the tag readerof this invention.

FIG. 5 is a cross-sectional view taken along line 5-5 of FIG. 4.

FIG. 6 is a vertical cross-sectional view taken through the scanningphototransducers and the lower ends of the illuminating optical fibers.5

FIG. 7 is a plan view of the timing disc.

FIG. 8 is an enlarged plan view of a portion of the timing disc of FIG.7, showing the relationship of the peripheral optical slots. 7

FIG. 9 is a plan view of a tag useful in conjunction with thedescription of the operation of the embodiment of the invention depictedin FIGS. 10A and 10B.

FIGS. 10A and 10B collectively are a schematic diagram of one preferredform of logic circuit suitable for use with the reader of thisinvention.

FIG. 11,is a plot of the waveform, as a function of time, of signals ata number of points in the circuit of FIGS. 110A and 10B.

FIG. 12 is a plan view of a tag useful in conjunction with thedescription of the operation of the embodiment of the invention depictedin FIGS. 13A and 13B.

FIGS. 13A and 13B collectively are a schematic diagram of anotherpreferred form of logic circuit suitable for use with the reader of thisinvention.

FIG. 14 is a plot of the waveform, as a function of time, of signals ata number of points in the circuit of FIGS. 13A and 138.

GENERAL DESCRIPTION As shown in FIG. 1, the preferred embodiment of thisinvention includes a tag reader 9 having a housing 10 which encloses thevarious operating components of the reader to be described in detailhereafter. The housing 10 is preferably formed in two complimentaryhalf-sections 10A and 10B, fabricated of cast aluminum, molded plasticor other suitable lightweight material, and contoured to permit it to becomfortably grasped by the users hand.

Projecting from the lower end of the housing 10 of the reader 9 is aretractable projection, plunger or probe 12. The lower end or tip 13 ofthe probe 12 is adapted to engage an aligner, such as a centrallydisposed hole 11, formed in a tag 14 which is attached to merchandise20, for example, articles on sale in a department store. Engagement ofthe tip 13 and hole 1] permits circularly arranged machine readable orphotosensible information 15, such as the price of the merchandise and aphotosensible start mark 27 imprinted on a surface 19 of the tag 14 toautomatically register with concentric circular scan paths of a pair ofsuitable circularly movable scanning phototransducers (not shown in FIG.ll) located within the lower portion of the housing 10 when the tag ispositioned at a. read station 16, that is, when the information-bearingsurface 19 of the tag 14 and the lower face 16 of the housing arerelatively moved into contact.

The lower central section of the housing 10 has a flush mountedindicating lamp 17. The lamp 17 is adapted to become illuminated whenthe reader 9 has completed reading a tag 14 properly positioned at theread station 16, thereby providing the operator with a visual indicationthat the tag reading cycle has been completed. The upper end of thehousing 10 is provided with an electrical cable 18 in which arepositioned the necessary wires for providing power to the variousoperating components of the reader 9, as well as for permitting theinformation 15 read from the tag 14 to be put to a suitable utilizationdevice, such as a cash register or centrally located data processingapparatus or computer.

In operation, the user grasps the central contoured section of thehousing 10 of the reader 9 and inserts the tip 13 of the probe 112 inthe central alignment hole 11 formed in the tag 14. The reader 9 and tag14 are relatively moved toward each other, preferably by moving thereader downwardly toward the tag, urging the probe 12 inwardly andpositioning the information-bearing surface 19 of the tag at the readstation 16. With the tag 14 and reader 9 so oriented, the circularlyarranged information 15 which is symmetrically disposed about thecentrally positioned hole 11 and the start mark 27 are automaticallyproperly registered with the circular scan paths of the phototransducers(not shown in FIG. 1) contained in the reader. In addition, the probe 12is retracted. This provides an input to the reader control or logiccircuit (not shown in FIG. I) for the purpose of initiating circularscanning motion of the transducers, and thereby commencing the tagreading operation.

Upon completion of the tag reading operation, which occurs when thetransducers have fully scanned the circularly arranged information 15,the indicating lamp 17 becomes illuminated, visually advising theoperator that the tag reading operation has been completed. The operatorthen removes the reader from the operative reading position with respectto the tag 14, preferably by lifting the housing 10 upwardly.

TAG

Considering in more detail a preferred form of tag 14 suitable for usewith the reader 9 of this invention, reference is made to FIG. 2.Referring to this figure, tag 14 is shown to include a circular sheet ofprinting stock 211 constituting the body of the tag. The printing stock21 is preferably constituted of paper, although other materials may beused, such as light gauge metals or foils, wood strips, plastic sheetsand the like. The printing stock 21 is provided with theinformation-bearing surface 19 which is adapted to receive an imprint ofthe photosensible information 15 and, if desired, a humanly intelligibletranslation 22 of the information. Preferably, the information-bearingsurface 19 is integral with the print stock 21, although it iscontemplated that the information-bearing surface 19 may comprise, forexample, a thin piece of paper laminated or adhered to a suitablesupport material or substrate such as wood, plastic, metal and the like,the paper and substrate in combination comprising the tag.Alternatively, the information-bearing surface 19 may comprise a printreceptive surface on the merchandise itself or on a package in which themerchandise is contained.

The humanly intelligible translation 22 may be omitted under certainconditions. For example, if it becomes necessary to reduce the size ofthe tag to a minimum, the translation may be omitted and the size of thetag reduced accordingly. Typically, a tag such as that shown in FIG. 2which includes the translation 22 is approximately 1% inches indiameter.

Also included in the preferred embodiment of the tag 14 is the aligner11, which preferably is a through hole, although it may be in the formof a blind hole, depression or dimple which does not extend entirelythrough the print stock 21. The function of the hole 11 is to engage thetip 13 of the projecting probe 12 for the purpose of automaticallyregistering the circularly arranged information with the transducers ofthe reader 9 when the tag 14 is at the read station 16.

The machine-readable information 15 includes an inner ring containingthe start mark or bit 27 and an outer information or data ring 26. Theinformation or data ring 26 is divided into 62 equally circumferentiallyspaced and contiguous information or data bit positions 31, each ofwhich is adapted to receive a photosensible mark 50. Of the 62information bit positions 31, one-is left blank and one is used incombination with start mark 27 to control the reader. Specifically,information or data bit position 32 is left blank and information ordata bit position 33, which is aligned with the start mark or bit 27, isprovided with a photosensible mark 34. Information bit position 32 isleft blank merely because its use is unnecessary in an informationformat having 12 characters, each with five information bits, to bedescribed. The photosensible mark 34 in combination with the start mark27 establishes a reference for the beginning of the information 15, andwhen sensed by the transducers of the reader 9, initiate the readingoperation. The remaining 60 information marks of ring 26 are dividedinto 12 contiguous character groups 37-48 each having five informationor data bit positions A-E.

The character groups 37-48 are encoded by placing the photosensiblemarks 50 in the various information bit or data positions 31 as dictatedby the particular code being used.

Preferably, the character coding scheme depicted in FIG. 3 is utilized.In the preferred coding scheme depicted in FIG. 3, the information ordata bit positions 31 have positionable significance in the sense thatthe positions A-E of each character group 37-48 are weighted.Specifically, the first data position A of each character group 37-48 isassigned a value of l, the second data position B of each charactergroup is assigned a value of 2, the third data position C of eachcharacter group is assigned a value of 4, the fourth data position D ofeach character group is assigned a value of8, and the fifth dataposition E of each character group is assigned a value of 0, the fifthposition being a check position.

If, for example, it is desired to encode a character group with thenumber I, a photosensible mark 50 is placed in data position A and dataposition E. Similarly, if a character group is to be encoded with thenumber 2, a mark 50 is placed in the second data position B and thefifth data position E. In any given character group the value of thenumber encoded is equal to the sum of the values associated with thosebit positions in which marks are placed, except for the number 0 whichis encoded by placing a mark in bit positions B and D and except for thenumbers 11-15 which have other than numerical significance. Illustrativeof such nonnumerical code significance is character group 46 in whichthe photosensible marks correspond to the word FOR," and the charactergroup 37 in which the marks correspond to the words START MESSAGE.'.

As those skilled in the art will understand, it is not necessary thatall of the 12 character groups 37-48 be encoded. Nor is it necessarythat the character groups be encoded in accordance with the codedepicted in FIG. 3. It is contemplated that other coding arrangementsmay be used such as conventional binary wherein the bit positions A, B,C, D and E of each code group correspond to the weighted binary values1, 2, 4, 8, and 16, respectively. Further, it is not necessary that theencoding be numerical. Alphabetical or alpha-numerical coding may beused, as well as symbolism. It is also not necessary that the 60 bitpositions of information ring 26 having encoded data be divided into 12five-bit characters. Other character groupings are possible, such as 15four-bit characters, l0 six-bit characters, etc.

The humanly intelligible translation 22 of coded information in ring 26is divided into 12 juxtaposed character positions 51-62 corresponding tothe 12 character groups 37- 48 of the information ring. Assuming thenumber 640385, an inventory number identifying a merchandise item, isencoded in the character groups 38-43, the character positions 52- 57contain, as shown in FIG. 2, the humanly intelligible Arabic numerals 6,4, 0," "3, 8" and 5." Likewise, if the bit positions 48-44 are encodedwith the information 10 FOR 89, which may for example indicate the priceof the merchandise, the character positions 62-58, respectively, willbear the humanly intelligible Arabic numerals I and "0, the word FOR,and the Arabic numerals 8 and 9.

READER Considered in more detail, the reader 9, which is shown moreparticularly in FIGS. 4-7, includes the housing 10 enclosing astationary frame or support 99 and a generally symmetrical scanningassembly 100. The assembly 100 is disposed coaxially relative to theprobe 12 and is mounted in framesupported ball bearings 101 and 102 forrotation by a stationarily mounted scan motor 103. The motor 103 isconnected by wires (not shown) to logic circuits 200 or 400, as the casemay be, for energization when the probe is inserted into the readerhousing 10. The scanning assembly 100 carries in its lower end suitablephototransducing means 97 and 98, to be described. The phototransducingmeans 97 and 98 move in concentric circular scanning paths inregistration with the information ring 26 and the ring 25 containing thestart mark 27, respectively, of tag 14 properly positioned at the readstation 16, that is, with its information-bearing surface 19 in contactwith a stationarilymounted transparent annular window 105. Associatedwith the central portion of the scanning assembly 100 is timing means107 which, in a manner also to be described, generates a predeterminednumber of timing or clock pulses for each data position 31 of theinformation ring 26 in synchronism with the sensing of the datapositions by the phototransducer-97.

The frame or support 99, which is secured to the housing 10 by fasteners(not shown), is a uniquely configured casting, molding or stampinghaving a plurality of suitably positioned locating surfaces forsupporting and positioning the various components of the reader inoperative relationship with each other. The frame 99, more specifically,includes a lower portion 110 having a central bore 111 thereinconfigured to accommodate the rotatable scanning assembly 100.Positioned within the bore 111 at its upper end is the bearing 101 whichlocates and rotatably mounts the upper end of the scanning assembly 100.A circular clip 112 seated in a circumferential groove in the bore 111locates the lower portion of bearing 101 while an annular disc or collar113 secured to the frame surface 114 locates and retains the bearing.Positioned within the bore 111 at its lower end is the bearing 102 whichlocates and rotatably'mounts the lower end of the scanning assembly 100.A circular clip 115 secured in a circumferential groove formed in anouter sleeve 116 of the scan assembly 100, in combination with ashoulder 117 also formed on the outer sleeve, locates and mounts thebearing 102. The frame 99 also includes an upper portion 118 whichmounts the scan motor 103.

The scanning assembly 100 considered in more detail includes, as shownparticularly in FIG. 4, the generally hollow cylindrical sleeve 116having a stepped diameter outside surface. The sleeve 116 is mounted forrotation with the inner races of the ball bearings 101 and 102 inresponse to rotation by the scan motor 103.

A pair of slip rings and 136, as shown in FIG. 4, are positioned aboutthe sleeve 116 and separated from .each other and from the outer surfaceof the sleeve by a suitably configured insulating spacer 138 which issecured to the outer surface of the sleeve. The slip rings 135 and 136cooperate with the free ends of suitably disposed stationary leaf springcontacts 139 and 140, the other ends of which are secured in astationary insulative support 141 mounted in the frame section 110.Electrically connected to the slip rings 135 and 136 are wires 143 and144, respectively, which extend downwardly in a vertical slot 145 formedin the periphery of the sleeve 116 for ultimate connection toilluminating means or scan lamp 183, for irradiating the surface 19 of atag 14 located at the read station 16 in a manner to be described. Thecontacts 139 and 140, in addition to being in electrical contact withthe slip rings 135 and 136, are also electrically connected to theassociated logic circuit 200 or 400, as the case may be, by suitablewires (not shown) enabling power to be transmitted to the illuminationmeans or scan lamp 183 when the probe 12 is inserted into the readerhousing.

A stepped outside diameter lower inner sleeve 150, as shown in FIG. 4,is positioned within the hollow sleeve 116. The inner sleeve 150 has anexternally threaded lower end which interfits and engages an internallythreaded bore 179 of a transducer mounting block 180 for securing thesleeves 116 and 150 relative to the block. The lower inner sleeve 150has an external shoulder 151 which cooperates with an internal shoulder152 formed on the sleeve 116 for properly locating the sleeves 116 and150 with respect to each other. The sleeve 150 further includes a smalldiameter lower bore 153 and a large diameter upper bore 154.

As depicted in FIG. 4, the probe 12, in addition to the tip 13, includesa lower shaft portion 155 and an upper shaft portion 156 separated by alarger diameter portion or collar 157. The lower shaft portion 155 ofthe probe 12 is located by, and axially shiftable within, the smalldiameter bore 153 of the lower inner sleeve 150. The upper shaft portion156 of probe 12 is located by, and axially shiftable within, a bore 158of an upper inner sleeve 159. A compression spring 161 is placed aboutthe upper shaft portion 156 of the probe 12 between a shoulder 163 ofsleeve 159 and the collar 157 for biasing the probe 12 downwardly to theextended probe position shown.

Cooperating with the upper end 167 of the probe 12 is a probe switch 165stationarily mounted by a bracket 166 to the frame 99, as shown in FIG.6. The switch 165 has a vertically shiftable, downwardly biasedactuating button 165A adapted to be shifted upwardly. to complete anelectrical circuit through the switch when the probe 12 is inserted intothe reader as a consequence of placing a tag 14 at the read station 16.Upward movement of button 165A for switch actuation in response to probeinsertion is accomplished by means of a pivotal yoke 168, and avertically shiftable sleeve 169 slideably encircling the sleeve 159. Theyoke 168 has legs 170 and 171, which at a point intermediate their endsextend closely adjacent the periphery of sleeve 169 and in overlyingrelationship to a flange 172 extending radially from the bottom end ofthe sleeve. At one end the yoke legs 170 and 171 are pivotally mountedby a pin 173 to a frame 99. At the other end yoke legs 170 and 171 arejoined by a central web or lip 174 which underlies the switch actuatingbutton 165A. Lip 174 is adapted to vertically shift the button when theyoke 168 is pivoted by engagement of the sleeve flange 172 in responseto upward movement of probe 12. A transverse pin 175 with ends anchoredin holes 176 formed in sleeve 169 extends through diametral oversizedslots 177 in sleeve 159.

In operation, when a tag 14 is brought to read station 16, the probe 12is urged into the reader housing, causing the upper end 167 of the probeto abut and move upwardly the transverse pin 175. Vertical shiftingmovement of pin 175 raises sleeve 169, which in turn causes flange 172to abut and pivot clockwise yoke legs 170 and 171, lifting lip 174.Elevated lip 174 abuts and shifts button 165A, actuating switch 165. Theswitch 165 is suitably connected in logic circuits 200 and 400 forproviding an electrical signal when the probe position is changedbetween a retracted position and an extended position which, among otherthings, is used to control energization of the scan motor 103 and scanlamp 183.

The transducing section of the reader 9 which is contained in the lowerportion of the scanning assembly 100 includes the mounting block 180.The block 180, as shown in FIG. 4, has a small diameter bore 181 withinwhich the lower portion 155 of the probe 12 islocated and axiallyshiftable, and the large diameter bore"179 within which is threaded thelower portion of the sleeve 150 for locating the block 180 in itsoperative position. Formed in an upper radially extending portion 178 ofthe block 180 is a cavity (not shown) which receives the scan lamp 183.The cavity and lamp 183 function as a source of illumination forirradiating the information-bearing surface 19 of the tag 14 via a fiberoptic means 190 to be described. Within suitable slots formed in theradial portion 178 of block 180 are the lower ends of the pair of wireconductors 143 and 144 which interconnect the lamp 183 and the sliprings 135 and 136, respectively, for providing the lamp 183 with thenecessary electrical power.

The fiber optic means 190 include a set ofilluminating optical fibers190A and 1908 which transmit light from the lamp 183 to theinformation-bearing surface 19 ofa tag 14 properly located at the readstation 16. The illuminating optical fibers 190A and 1908 at their upperend 191 are grouped together and terminate at the cavity for the lamp,adjacent the lamp 183 where they are suitably clamped in position. Asbest seen in FIG. 5, the illuminating optical fibers 190A and 1908 attheir lower ends are divided into two separate groups 192A and 1928, and193A and 19313. The groups 192A and 1928, and 193A and 193B terminate inradially disposed, scanning apertures 194A and 1948, and 195A and 195Bformed in a disc 188 positioned at the read station 16. The disc 188 issecured to the lower extremity of the block 180 parallel to thetransparent window 105.

The scanning apertures 194A 194B, 195A and 195B are radially positionedwith respect to the probe 12 such that when a tag 14 is properly alignedand positioned at the read station 16, optical fiber groups 190A and190B illuminate the information ring 26 and the ring 25 containing thestart mark 27, respectively.

The phototransducers 97 and 98 are mounted in cavities and 121 formed indisc 188 and optically communicate with the information ring 26 andstart ring 25 of a tag 14 positioned at read station 16 viafunnel-shaped bores 122 and 123 interconnecting the cavities 120 and 121with sensing apertures 196 and 197 located adjacent the window 105. Thesensing apertures 196 and 197 are located intermediate the scanningapertures 194A and 1948, and 195A and 195B. The phototransducers-97 and98 may be of any suitable type. Phototransducers of the phototransist'ortype manufactured by Texas lnstruments, Incorporated, and designatedModel No. LS-600 have been found to be satisfactory.

As shown in FIGS. 1 and 5, electrical connections to thephototransducers 97 and 98 are preferably provided by means ofelectrical wires 125, 126 and 127, and a slip ring and brush assembly128. The wires and 127 have their lower ends connected to different onesof the phototransducers 97 and 98 and their upper ends connected toconductive slip rings 129 and 131, respectively. Wire 126 at its lowerend is connected to the other terminal of each of the phototransducers97 and 98 and at its upper end is connected to slip ring 130. Theconductive rings 129-131 are insulated from each other and from theblock and an annular spacer 65 positioned about the sleeve 116, and byannular insulative discs 66, 67, 68, and 69. Cooperating with theconductive rings .129, 130 and 131 are the free ends of conductive wirebrushes 71, 72 and 73 whose opposite ends are secured in an insulativebrush holder 74 stationarily mounted to the frame 99. The brushes 71-73are connected, in a manner to be described, to the logic circuits 200and 400 depicted in FIGS. 10 and 13 for transmitting signals between thetransducers 97 and 98 and the logic circuits.

Two illuminating fiber optic groups A and 1908 and two phototransducers97 and 98 are provided in the embodiment shown. in the event that it isdesired to provide an optional information ring on theinformation-bearing surface 19 of the tag 14 intermediate rings 25 and26, an additional fibre optic illuminating group and phototransducer maybe provided; in which case, an additional slip ring and brush are neededin the slip ring and brush assembly 128.

The timing means 107 for generating timing signals in synchronism withthe sensing of the circularly arranged photosensible mark receivingpositions 31 and the start mark 27, which is depicted more particularlyin FIGS. 4, 7 and 8, includes a stationary source of light or lamp 76mounted in a cavity 77 formed in frame 99, and a phototransducer 78 alsostationarily mounted on frame 99. The lamp 76 is connected by means (notshown) to the logic circuits 200 and 400 to permit energization of thelamp when the probe is inserted into housing 10. The transducer 78preferably is of the same type as transducers 97 and 98, although othersmay be used if desired, and is connected by means (not shown) to thelogic circuits 200 and 400 to provide timing or clock signals. The lamp76 and the phototransducer 78 are disposed such that a beam of light 80emanating from the lamp 76 and colliminated by lens 79 is directedtoward the phototransducer 78.

The timing means 107 further includes a light beam interrupter or timingdisc 81 shown more particularly in FIGS. 7 and 8. The interrupter 81 ispreferably annular, having an inner marginal portion 82 and an outermarginal portion 83. The interrupter 81 is fixedly mounted on a spacer84 secured to the outer surface of sleeve 116, and is positioned betweena clamp collar 85 surrounding the spacer 84 and an external flange 86formed on the periphery of the spacer 84. Thus, the timing disc 81rotates with the sleeve 116 and, hence, with the scanning assembly 100.

The outer marginal portion 83 of the timing disc'8l is provided with aplurality of light transmitting slots or apertures 87 separated fromeach other by opaque sections 88. The number and spacing of lighttransmitting slots 87 are such as to enable the light beam 80 emanatingfrom the lamp 76 to be transmitted to phototransducer 78 by adjacentslots 87 of the rotating disc 81 a multiplicity of times for eachsensing by the phototransducer 97 of a contiguous information or dataposition 31 of information ring 26. This enables the phototransducer 78to generate a multiplicity of electrical timing signals during thesensing of each data positions 31. Preferably, slots 87 are provided indisc 81 for each data position 31 in information ring 26. lnthepreferred embodiment wherein the timing disc 81 is driven at the sameangular speed as the scanning assembly 100 and, hence, at the sameangular speed as the fiber optic illuminating means 190 andphototransducers 97 and 98, the number and spacing of slots 87 aredesigned to correspond to a multiple, preferably a factor of 20, of thenumber and spacing of the information bit positions 31 formed in theinformation ring 26. Specifically, 1240 equally spaced slots 87 areprovided in the outer marginal portion 83 of the disc 81 correspondingto the 20 slots for each of the 62 information bits 31 formed in theinformation ring 26. With the number and spacing of the slots 87 soselected, each revolution of the timing disc 81 generates 1240 timingpulses, the pulses being generated as each slot 87 passes between thelamp 76 and the phototransducer 78, permitting the phototransducer to beilluminated by. the beam 80.

The number of timing signals generated per data position 31 isarbitrary. However, the accuracy with which the center of a dataposition can be selected by the logic circuits, to be described, forsampling data, is dependent on the number of timing signals per dataposition, the accuracy being greater within limits as the number isincreased. Accordingly, it is preferable to generate a sufficient numberof timing signals, for example, 20, per data position to insure a highdegree of accuracy. I

Generation of a timing signal by the phototransducer 78 in .response toirradiation by the beam 80 when a slot 87 passes 10 LOGlCCIRCUITEMBODIMENT 1 Structure The logic circuit 200 illustrated in FIGS.10A and 108 includes the normally open probe switch connected between asource of positive potential 199 and a driver circuit 198. The switch165 is adapted to be closed when the probe 12 is positioned in its innerposition by movement of a tag 14 to the read position 16 of the reader10. In the closed position, switch 165 energizes drivercircuit 198,which in turn energizes scan motor 103, scan lamp 183, and timing lamp76.

The circuit 200 also includes a start circuit 201 which is connected toreceive input signals from the data line 202, the start line 203 and theready to receive line 204. The data line 202 and the start line 203 areconnected to brushes 71and 73 of the reader 9and are responsive to theoutput signals of-the data ring scanning transducer 97 and to the startring scanning transducer 98, respectively. A positive electrical signal,herein defined as a logical l is produced on data line 202 and startline 203 when the data ring scanning transducer 97 and start ringscanning transducer 98, respectively, sense a photosensible data markand a photosensible start mark, respectively. The ready to receive line204 is responsive to a utilization device 205, such as a buffer memoryfor a computer, cash register or the like. A positive electrical signalappears on the ready to receive line 204 when the the utilization device205 is in a ready condition, that is, in a, condition wherein it isready to receive information produced as a consequence of a tag readingcycle.

The start circuit 201 includes a ready to receive flip-flop 206 havingan input terminal P which is connected to the ready to receive line 204.Flip-flop 206 provides at flip-flop output terminals Q and 6, which areconnected to lines 207 and 208, complementary positive and negativeoutputs when placed in a set condition upon receipt from the utilizationdevice 205, via a differentiator 196, of the positive ready to receivesignal on ready to receive line 204. .The ready to receive flip-flop 206also includes a reset terminal R con nected to a reset line 210. Theready to receive flip-flop 206 in response to a negative reset signal online 210 input to its reset terminal R placesthe flip-flop in a resetcondition, providing at terminals 0 and 6 connected to output lines 207and 208 negative and positive signals, respectively.

The ready to receive flip-flop 206 is preferably of the type marketed byTexas lnstruments, lnc., designated Model SN-7474. A detailed circuitdiagram for the ready to receive flip-flop 206 and a truth tabledescribing its operation are shown in FIGS. 25 and 20, respectively, ofcopending application for Improved Encoded Tag Reader in the name ofFrederic L. Rieger et al., filed Oct. 3, 1967, Ser. No. 672,629. Theentire disclosure of the foregoing Rieger et al. application isincorporated herein by reference.

The start circuit 201 also includes a NAND gate 211. The

NAND gate 211 has three input terminals connected to the data line 202,start line 203, and ready to receive line 204, via flip-flop 206, andprovides on NAND gate output line 212 a negative signal in response tothe simultaneous presence on the input lines 202-204' of positivesignals. A start flip-flop 214 is also included in the start circuit201. The flip-flop 214 is preferably of the type marketed by TexasInstruments, Inc., designated Model SN-7474. The start flip-flop 214 hasan input terminal P connected to the NAND gate output line 212, and anoutput terminal Q at which a positive signal is provided in response toa negative signal input to terminal P. A reset terminal R, alsoincluded, is connected to one of the complementary output terminals ofthe ready to receive flip-flop 206 via an inter 215. A negative signalinput to terminal R of start flip-flop 214 resets the flip-flop,therebyproviding at output terminal Q a negative signal. A negativeinput to terminal P of start flip flop 214, which represents thesimultaneous occurrence of positive signals on the data, start, andready to receive lines 202-204, respectively, places the flip-flop 214in a set condition, providing a positive signal at flip-flop outputterminal Q.

The start circuit 201 provides two principaL output signals, namely, anegative signal on line 212 and a positive signal on line 216 indicativeof the coincidence of positive signals on the data, start, and ready toreceive lines 202204. The positive output signal from the start circuit201 on line 216 is input directly to a clock signal NAND gate 219. NANDgate 219 is also responsive to positive clock signals on clock line 220connected to the timing or clock transducer 78. Under normal tag readingconditions, the start flip-flop 214 is in the set condition providing apositive signal on output line 216 from the time the start mark 27 issensed for the first time by the start ring scanning transducer 98 untilthe start mark is sensed for a second time following a completerevolution of the start ring scanning transducers. With an enablingsignal input to the clock signal NAND gate 219 from start circuit outputline 216 for an interval coextensive with a complete scanning revolutionbeginning and ending with sensing of the start mark 27 by the start ringscanning transducer, clock signals appearing on clock line 220 are gatedby NAND gate 219 for one complete revolution of the ticket scanningoperation beginning and end ing with the sensing of the start mark,thereby providing a train of positive clock pulses on line 221 via aninverter 222. A data mark width NAND gate 223 having its input terminalsconnected to line 212 via inverter 224 and to line 221, is provided. TheNAND gate 223 provides on its output line 225 a train of negative clocksignals, coextensive in duration to the width of the signal generated asa consequence of sensing the photosensible mark 34 of the data ringwhich is aligned with the start mark 27.

The logic circuit 200 further includes a data sampling circuit 230 whichis operative to sample data signals appearing on data line 202 forstorage in a memory unit 232 to be described later. The data samplingcircuit 230 includes a flipflop 233 which is utilized to provide on itsoutput line 229 a pulse train containing one-half the number of pulsescontained in the pulse train output from the data mark width gate 223 online 225. The flip-flop 233 has an input terminal CL connected to line225 for providing at coupled output terminals and K positive signals ata frequency one-half that of the frequency of the positive signals inputat terminal CL. The flip-flop 233 also has a reset terminal R connectedto a reset line 231 which functions to place the flip-flop in decadereset state in response to a negative signal input thereto, providing anegative signal at coupled output terminals Q and K. F lip-flop 233 ispreferably of the type marketed by Texas Instruments, lnc., designatedModel No. SN-7473. A detailed circuit diagram of such a flip-flop isshown in FIG. 27 and operates in accordance with the truth table of FIG.22 disclosed in the previously referenced Rieger et al. application.

The data sampling circuit further includes a decade counter 234 havingan input terminal CL and four output terminals A, B, C, and D,corresponding respectively to decimal digital values 1, 2, 4 and 8. Thedecade counter 234 provides positive output signals at terminals A, B,C, and D in a manner such that the algebraic sum of the valuesassociated with each terminal at which positive outputs appear equalsthe number of positive pulses input to the decade counter at terminalCL. For example, if only a single positive input pulse appears atterminal CL, a positive signal is output at terminal A representing thedecimal digital value 1. Similarly, if six positive pulses are input tothe decade counter 234 at terminal CL output signals appear at terminalsB and C representing the decimal digital value 6. The decade counter 234has a pair of reset terminals R connected to reset line 236 for placingthe decade counter 234 in a condition such that negative signals appearon output terminals A, B, C, and D, representing the digital value 0.The decade counter 234 functions to accumulate, and provide at theoutput terminals A, B, C, and D, a binary coded representation having avalue equal to one-half the number of clock pulses generated during theinterval defined by the width of the data mark 34 aligned with the startmark.

The data sampling circuit 230 also includes a decade counter 238 havingan input terminal CL output terminals A, B, C, and D, and a pair ofreset terminals R. Terminals CL, R, and A, B, C, D of decade counter 238function in the same manner as the similarly designated terminals ofdecade counter 234. lnput terminal CL of decade counter 238 is connectedto the line 221 on which appear clock signals during the tag readingcycle beginning and ending with the sensing of the start mark 27. Thedecade counter 238 counts all clock signals starting with the initialsensing of the start mark, providing at output terminals A, B, C, and Da partial representation of the number of clock signals, therepresentation being partial in the sense that the decade counter 238recycles every 10 clock pulses input thereto on line 221.

Decade counters 234 and 238 are identical in construction and preferablyare of the type marketed by Texas Instruments, lnc., designated ModelSN-7490.

Each of the decade counters 234 and 238 is provided with four inverters234-1, 234-2, 234-3, 234-4 and 238-1, 238-2, 234-3, and 238-4,respectively. The outputs of these inverters provide complementarysignals for the respective output terminals of the decade counter withwhich they are associated. For example, the signal at the outputterminal A of inverter 238-ll is the inverse of the signal at outputterminal A of decade counter 238.

The data sampling circuit 230 also includes a flip-flop 240. Theflip-flop 240, like the flip-flop 233, is preferably of the typemarketed by Texas Instruments, lnc., designated Model SN-7473. Theflip-flop 240 has an input terminal CL and a reset terminal R. Flip-flop 240 also includes terminals 0 and K which constitute a firstcoupled output terminal and terminals J and 6 which constitute a secondcoupled output terminal. Coupled output terminals K-Q and 6-] providecomplementary output signals. A negative signal input to terminal Rresets the flip-flop 240, providing positive and negative signals atcoupled output terminals J-6 and 0-14, respectively. The input terminalCL of flip-flop 240 is connected via line 242 to the output of NAND gate241, NAND gate 241 in turn having its inputs connected to terminals A,B, C, and D of inverters 238-1, 238-2, 238-3 and 238-4, respectively.NAND gate 241 connected in the manner described provides a negativeinput signal on line 242 to the terminal CL of flip-flop 240 every l0thclock pulse starting with the second clock pulse gated by NAND gate 219,namely, at clock counts 2, 12, 22, 32, 42...The flip-flop 240 inresponse to these negative input pulses, provides negative output signallevels at coupled output terminals 6-] during clock count intervals 2--12, 2232, 4262...,and positive output signal levels during clock countintervals 12-22, 32--42, 5262...Since the output signal at coupledoutput terminal K-Q is complementary to the output signal at coupledterminal 6-], positive signal levels are provided at coupled outputterminal K-Q during clock count intervals 2232, 4252, 6282...,andnegative signal levels are provided during clock count intervals 32-42,52-62, 7282...The function of the output signals at coupled outputterminals K-Q and 1-0 will become apparent hereafter.

The data sampling circuit 230 further includes eight multiinput NANDgates 251, 252, 253, 254, 255, 256, 257, and 258. Each of the NAND gates251-258 has four inputs 251-1 to 251-4, 252-1 to 2524...258-1 to 258-4,respectively, connected to various of the outputs A, B, C, D andinverted outputs A, B, C, and D of decade counter 238. The connectionsare such that all four of the inputs 251-1 to 25l-4,252-l to252-4...258-1 to 258-4 of a given NAND gate 251--258, respectively, aresimultaneously positive for one particular clock count once every 10clock pulses, the one particular clock count during which each NAND gatehas its four inputs simultaneously positive being different for eachNAND gate. The eight different clock counts, which are separated fromeach other by 10 clock pulses, during which the four inputs 251-1 to251-4, 252-1 to 252-4...2581 to 258-4 of NAND gates 25l258,respectively, are simultaneously positive, collectively correspond tothe center points of data signals of all possible widths.Specifically,-the four inputs 251-1 to 251-4, 252-1 to 252-4...25 8-1 to258-4 of NAND gates 251-258 are simultaneously positive at clock countsof 3, 4, 5, 6, 7, 8, 9, and l0, respectively; at clock counts of 13, l4,l5, l6, I7, 18, I9, and 20, respectively; at clock counts of 23, 24, 25,26, 27, 28, 29, and 30, respectively, corresponding to the center pointsof successive data signals having widths of 6, 8, l0, l2, l4, l6, l8 and20, respectively.

The other four inputs 251-5 to 251-8, 252-5 to lilrL fi-flqis areconnected. inva o s. c in tions to the outputs A, B, C, D or invertedoutputs K, F, C, D of decade counter 234. Since the decade counter 234is fed clock pulses only during the interval coextensive with thesensing of the start mark, the decade counter 234 does not recycle, butrather remains fixed at one count corresponding to one-half the numberof clock pulses generated during the width of the data bit. Thus, forany one data signal width, one and only one set offour of these inputs251-5 to 251-8, 252-5 to 2528...258-5 to 258-8 will have all its inputsin a positive condition. Stated differently, for any given data signalwidth, one and only one of the NAND gates 251-258 is enabled by theoutputs A, B, C, D, and inverted outputs Z, 8, C, of decade counter 234.The particular one of the NAND gates 251-258 which is enabled dependsupon the precise width of the data signal. For example, NAND gates 251,252.258 are enabled for data signals having widths of 6, 8...20 clockcounts, respectively. While each of the NAND gates 251 258 has itsinputs 251-1 to 251-4, 252-1 to 252-4...258-l to 258-4 simultaneouslyrendered positive by decade counter 238 once every 10 clock counts, theclock counts being different for the different NAND gates, because onlyone of the NAND gates is enabled by the decade counter 234 only one ofthe NAND gates produces a cyclic output every 10 clock counts. However,the NAND gate 251-258 which does produce an output every 10 clock countsproduces an output which, for alternate outputs, occurs at a timecoincident with the center point of the data signal.

For example, assuming the width of the data signal is six clock countswide, NAND gate 251 is partially enabled by the decade counter 234 whichhas stored therein a count of three corresponding to one-half the widthof the six clock count wide data signal. With NAND gate 251 partiallyenabled by decade counter 234, an output is produced from this NAND gateevery 10 clock counts by reason of the cyclic operation of decadecounter 238. The exact time of the output from NAND gate 251 is at clockcounts of 13, 23, 33, 43 Because decade counter 238 cycles twice foreach data position, the frequency of the output of NAND gate 251 istwice that required for data sampling, the signals output therefrombeing spaced at 10 clock count intervals instead of clock countintervals corresponding to clock count interval of a data position.However, alternate outputs of NAND gate 251 occurring at clock counts of23, 43, 63, 83...coincide with the center of the first, second, third,fourth...data positions.

As a further illustration, if the width of the data signal is equal to16 clock counts, NAND gate 256 is partially enabled by decade counter234 which has stored therein a count of eight corresponding to one-halfthe number of clock pulses occurring during the interval defined by thel6 clock count wide data signal. NAND gates 251255, 257 and 258 are notpartially enabled by the decade counter 234. Since only NAND gate 256 ispartially enabled by decade counter 234, cyclic outputs at twice therequired data sampling frequency are produced only by this NAND gate.These outputs from NAND gate 256 occur each time the four signals fromdecade counter 238 to inputs 256-5 to 256-8 of NAND gate 256 are allpositive, namely, each time a count of eight is accumulated in decadecounter 238 which occurs at clock counts of 18, 28, 38, 48...The secondoutput from NAND gate 256 occurring at clock count 28, and alternateoutputs thereafter, coincide with the centers of I 16 clock count widedata signals should such be present during the first, second,third...data positions. The first output from NAND gate 256 occurring atclock count 18, and alternate outputs thereafter, occur between datasignals in the first, second, third data positions should there be suchsignals.

Suppression of the surplus first, third, fifth, seventh...nega-- tiveoutputs from the one NAND gate 251-258 which is enabled by decadecounter 234 is provided by the flip-flop 240, acting in combination withsample NAND gate 260. Specifically, sample NAND gate 260 is connectedvia NOR gate to the NAND gates 251258 and, accordingly, one input to thesample NAND gate 260 is the cyclic negative output of the one NAND gate251-258 which'is partially enabled by the decade counter 234. Thiscyclic input to sample NAND gate 260 occurs at twice the desired datasampling rate of once per 20 clock pulses. The sample gate 260 also hasone input connected to flip-flop 240 which, as will be recalled,switches state every l0 clock counts, namely, at clock counts 2, 12, 22,32...By reason of the connection of one of the inputs of sample NANDgate 260 to the output of flip-flop 240, the sample NAND gate 260 ispartially enabled by the positive output of flip-flop 240 foralternative 10 clock count intervals, namely,

is partially enabled for clock count intervals 2232, 42-52,

6272....The 10 clock count intervals during which the sample NAND gate260 is partially enabled by the positive output of flip-flop 240coincide with the intervals during which data signals occur. When thesample NAND gate 260 is partially enabled by the flip-flop 240 which, asindicated occurs during intervals when data signals occur, alternateones of the cyclic positive signals output from NOR gate 262 whichcoincide with the centers of the potential data signals, are effectiveto gate or sample data input to the sample NAND gate on data line 202,producing sampled data signals on line 261. The positive output from NORgate 262 occurring between potential data signals cannot function tosample data on line 202 by reason of the NOR gate output beingeffectively inhibited, suppressed, or blocked by the negative signalinput to sample NAND gate 260 provided by flip-flop 240 occurring duringintervals when data signals are not potentially present.

The memory unit 232 includes a five-stage or position character storagecircuit 265 comprising five storage devices or flip-flops 271275, eachof which is preferably of the type marketed by Texas Instruments, lnc.,designated Model SN-7474. F lip-flops 27l -275 each have two terminals Pand 6 which are connected to each other, and an input terminal Rconnected to a reset line 276. When a negative signal appears on resetline 276, which occurs after each character is read by the data scanningtransducer, those storage devices 271-275 in the set conditioncorresponding to the storage of a logical 1" are switched to the resetcondition, providing negative signals at their output terminals-Q and ontheir respective output lines 281285. The storage devices 271-275further include sample data input terminals CL each connected to thesample data line 261 constituting the output of the sample NAND gate260. When a negative signal on sample data line 261 is present whichoccurs when a photosensible mark in the information ring is sensed byinformation ring scanning transducer 97, and when the storage device isprimed by a positive signal input to a priming terminal D, the storagedevice is switched from the reset state corresponding to a logical 0" tothe set state corresponding to a logical l producing a positive signalat the output terminal Q. A positive priming signal at terminal D offlip-flops 271-275 is necessary to permit the flip-flops to switch fromthe reset state in response to a negative sample data input at terminalCL.

The memory unit 232 further includes five NAND gates 291-295 each havinga first input terminal connected in common to a reset line 231, and asecond input terminal connected respectively to the storage deviceoutput lines 281- 285. When primed storage devices 271-275 are switchedfrom the reset state by the presence of negative signals at their inputterminals CL provided by the sampled data line 261, the positive outputsproduced at terminals Q and present on output lines 281-285 are gatedthrough their associated normally enabled NAND gates 291295 producingnegative signals on the NAND gate output lines 296-3110. The negativesignals in turn are input to inverters 3111-305, producing positiveoutputs which constitute the output from the memory unit 232 to theutilization device 205.

A five-position ring counter generally indicated by the referencenumeral 310 is included in the memory circuit 232. The ring counter 310includes five flip-flops 315, 316, 317, 318 and 319 which aresequentially stepped by stepping pulses from a sweeping circuit 320 tobe described to successively enable different ones of the storagedevices 271-275 in synchronism with the successive sensing of positionsA-E of the character groups 37-48. The flip-flops 315-319 preferably areof the type marketed by Texas instruments, lnc., designated Model811-7473.

Flip-flops 315-319 each hav an output terminal Q connected via 11185321,3 2 2, 323, 324, and 325, respectively, to the priming terminal D of theflip-flops 271-275, respectively, and a 6 terminal connected via lines326, 327, 328, 329 and 330, respectively, to the K or priming terminalof flipflops 316, 317, 318, 319, and 315, respectively. The connectionof the terminal and 6 terminal of the ring counter flipflops 316-319 topriming terminals .1 and K of successive flipflop stages thereoffacilitates priming or enabling of successive ring counter flip-flopswhen the preceding flip-flops are in the set condition, providingnegative and positive outputs at their 0 and 6 terminals. The connectionof the 0 terminal of ring counter flip-flops 315-319 to the D terminalof memory flipflops 271-275 facilitates successive priming or enablingof the memory flip-flops when the ring counter flip-flops aresuccessively in the set condition, providing positive signals at their 0terminal. The ring counter flip-flops 315-319 each have an inputterminal CL connected via a line 338 to the counter stepping circuit320. A negative signal from the counter stepping circuit 320 input tothe terminal CL ofa flipflop 315-319, assuming it is primed by positiveand negative signals at its terminals .1 and K, sets the flip-flop,producing positive and negative signals at output terminals 0 and G. inaddition, each of the flip-flops 315-319 has a reset terminal R which isconnected to the reset line 231. A negative signal at terminal R resetsthe ring counter flip-flops 3115-319 producing negative and positiveoutput signals at terminals 0 and U.

The ring counter 310 further includes a flip-flop 333 having an inputterminal R connected to reset line 231, an input terminal P connected tothe 6 terminal of flip-flop 315, and an output terminal 0 connected viaan inverter 331 to the terminal of flip-flop 315. The flip-flop 333 ispreferably of the type marketed by Texas Instruments, Inc., designatedModel SN-7474, and functions in combination with the inverter 331 toprime the first ring counter stage flip-flop 315 when the flipflop 333is reset at the end of a complete tag reading cycle thereby enablingflip-flop 315 to be placed in its set condition in response to the firststepping signal from the stepping circuit 320 occurring immediatelyprior to the scanning of the first data position A of the firstcharacter group by the data ring transducer 97.

The stepping circuit 320 includes a NAND gate 335 having four inputsconnected to the output or inverted output terminals of the decadecounter 238 in a manner such that an output is produced from NAND gate335 once every 10 clock counts, preferably at clock counts 8, 18, 28,38, 48...The output of the NAND gate 335 is input to a NAND gate 336 viaan inverter 337. The NAND gate has as its other input the coupled 1-6output of flip-flop 240 which, as indicated previously, is negativeduring the clock count intervals 2- 12, 22- 32, 42-52...and positiveduring the clock count intervals 12-22, 32-42, 52-62... The combinationof the input to NAND gate 336 from inverter 337 occurring once every 10clock counts and the input to NAND gate 336 from flip-flop 240 which isalternately switched from positive to negative every 10 clock countseffectively causes alternate outputs from inverter 337 to be inhibitedor suppressed, providing on NAND gate output line 338 a negative signalprior to the occurrence of the scanning by the data ring transducer ofevery data position of the tag. These signals present on NAND gateoutput line 338 occurring at 20 clock count intervals function to stepthe ring counter 310 once per data position at a point in time slightlyprior to the alignment of the data ring scanning transducer 97 with thedata position of the information or data ring.

A character readout circuit 340 is provided to reset the memoryflip-flops 271-275 after each character has been scanned to facilitateparallel readout of the information stored during that character scan.The character readout circuit 340 includes a NAND gate 341 having fourinputs connected to the outputs or inverted outputs of the decadecounter 238 in a manner such that pulses are output from NAND gate 341every other of which occurs at a time shortly following the storage inmemory flip-flop 275 of the last data position of the character beingscanned. Preferably the NAND gate 341 is connected to provide outputsignals at clock counts of 3, 13, 23, 33....,the useful clock countsbeing 113, 213, 313, 413...The output of NAND gate 341 is input to aNAND gate 342 via an inverter 343. The other input to the NAND gate 342is derived from the flip-flop 240. To suppress the undesired outputpulses of NAND gate 341 the NAND gate 342 is provided. The input of NANDgate 342 is connected to the flip-flop 240 in a manner such that theoutputs from inverter 3413 occurring at counts 3, 23, 43, 63...aresuppressed, the NAND gate outputs occurring at times 13, 33, 53,73...being gated via inverter 344 to a NAND gate 345. The NAND gate 345has as its other input the output provided at the Q terminal of ringcounter flip-flop 319, which output functions to suppress all signalsinput to NAND gate 345 from inverter 344 except those occurring shortlyafter sensing the last data position E of each character, namely, tosuppress all pulses except those occurring at times 113, 213, 313,413...Ring counter flip-flop 319 is switched to the set condition bypulses from the stepping circuit 320 on line 338 on clock counts of 98,198, 298, 398...-and is switched to the reset condition on counts of118, 218, 318, 418...NAND gate 345 therefore provides an output atcounts of 113, 213, 313, 413...This output is input to NOR gate 346which in turn is connected to an inverter 347 to provide a reset signalto the memory flip-flops 271-275 at counts of 1 13, 213, 313,413...,producing a parallel readout of the information stored in theseflip-flops shortly following scanning of data position E by the d-ataring transducer 97, in the manner described previously.

A parity error detector circuit 350 is provided and includes a flip-flop351. The flip-flop 351 preferably is of the type marketed by Texaslnstruments, lnc., designated Model SN-7473. Flip-flop 351 has a resetterminal R connected to the reset line 231, an input terminal CLconnected to the sample data line 261, and coupled K-Q terminalsconnected to one input terminal of a NAND gate 352. The other inputterminal is connected to the NOR gate 346. At the start of a tag readingcycle, flip-flop 351 is in the reset condition providing negativesignals at coupled output terminal K-Q. The first logical 1" data signalof the first character input to terminal CL of the flip-flop 351switches the flip-flop, providing a positive signal at coupled outputterminal Q-K. if another logical 1 does not occur during the scanning ofA through E of the first character group, the coupled Q-K output offlip-flop 351 remains positive. This positive output produces an outputfrom NAND gate 352 when a positive signal is output from NOR gate 346following completion of scanning of the first character group. Theoutput from NAND gate 352 signals a parity error, providing a signal toNOR gate 355 which produces a system reset signal on line 236.

if during the scan of the first character A a second logical 1 issensed, a second negative data signal corresponding to the secondlogical 1 is input to terminal CL of flip-flop 351, returning theflip-flop to its reset state. In the reset state, a negative signal isinput to the NAND gate 352 preventing the NAND gate from providing aparity error output signal when the NAND gate is pulsed by the outputfrom NOR gate 346 provided at the end of the character scan. Similarly,if during a character scan an odd number orlogical lsa is sensed andinput to the flip-flop 351, upon completion of the character scan whenthe NAND gate 352 is pulsed by the output of NOR gate 346 a parity errorsignal is input to the NOR gate 355 to produce a system reset signal online 236.

A character counter 360 is provided, and includes a duodecade counter361. The counter 361 is preferably of the type marketed by TexasInstruments, lnc., designated Model SN-7492. Counter 361 has a pair ofreset terminals R which when provided with a positive reset signal online 236 resets the counter to a count of zero. Counter 361 also has aninput terminal CL responsive to the positive output of a NOR gate 362which occurs once per character as the characters are read out of thememory flip-flops 271-275 in parallel. A NAND gate 363 responsive to theoutputs of the duodecade counter 361 via inverters 364, 365, 366 and 367provides a negative output to an inverter 368 in response to the entryinto the duodecade counter of 12 positive pulses.

The positive output from inverter 368 which is produced as a consequenceof the successive readout of 12 characters from the memory flip-flops271-275 is input to a NAND gate 370 of a reset circuit 371. NAND gate370 has as its other two inputs the inverted output of NAND gate 211 viainverter 224 and the priming output at terminal of the fourth ringcounter position flip-flop 318. A negative output is produced from NANDgate 370 indicating that the tag has been properly read when threeconditions simultaneously occur, namely, when the character counter 360provides a positive output indicative of the reading out of 12characters from the character storage circuit 265, when a positivesignal from NAND gate 211 is provided indicating that the start mark 27has been sensed a second time by the start ring scanning transducer 98,and when a positive priming signal from the fourth ring counterflip-flop 318 is provided indicating that the 64th data position on theinformation ring of the tag is aligned with the information ringscanning transducer 67.

The reset circuit 371 also includes the NOR gate 355. NOR gate 355 isresponsive to the output from NAND gate 352 of the parity error detector350, the output of the plunger or aligner switch 165 provided on line373, and the output from a message complete NAND gate 370 indicatingcompletion of a proper tag reading cycle. NOR gate 355, in response tocompletion ofa proper reading cycle, a parity error, or movement of theplunger or aligner 12 from the retracted position, produces a positiveoutput on line 236 and an inverted or negative output on line 210 viainverter 374. The positive and negative signals on lines 236 and 210collectively constitute system reset signals.

The reset signal on line 210 functions to reset the ready-toreceiveflip-flop 206. Resetting of flip-flop 206 disables NAND gate 211, whichin turn disables NAND gates 370 and 223 via inverter 224. Resetting offlip-flop 206 also resets start flip-flop 214 via inverter 215, which inturn disables NAND gate 219. Resetting of flip-flop 206 further operatesto reset flip-flops 351, 233, 315-319, 240, 333, and 271-275 via NORgate 346, inverter 215, and inverter 347, as well as to disable NANDgates 291-295. The reset signal on line 236 resets counter 361, counter234, and counter 238.

A complete read indicating circuit 380 is provided to illuminate thecomplete read indicator lamp 17 mounted in the reader upon completion ofa tag reading operation. The complete read circuit 380 includes aflip-flop 381. The flipflop 381 is preferably of the type marketed byTexas lnstruments, lnc., designated Model SN-7474. The flip-flop 381 hasan input terminal P responsive to the output from the message completeNAND gate 370 indicating that a message has been properly read, and areset terminal R responsive to the probe or aligner switch signal line373. The flip-flop 381 further includes an output terminal 0 connectedto the message complete indicating lamp 17 for providing a positivesignal for illuminating the lamp upon completion of a proper reading ofthe tag. The signal provided at terminal Q is rendered negative toextinguish the lamp in response to anegative signal input to resetterminal R as a consequence of a removal of the ticket from the readstation and the consequent extension of the probe or aligner, followingcompletion of a proper reading cycle.

Operation When the tag 14 is brought to the read position or station 16,aNd the probe 12 inserted into the readerhousing 10, switch 165 isclosed. Closing of switch 165 energizes driver circuit 199, in turnenergizing scan motor 103, scan lamp 183 and timing lamp 76. Closing ofswitch 165 also causes a positive signal to be input to NOR gate 355,which in turn provides a negative signal on line 236 and a positivesignal via inverter 374 on line 210. These signals remove the systemreset signals previously existing on lines 210 and 236, permitting thevarious system counters and flip-flops to be placed in a set condition.Specifically, when the system reset signal is removed from line 210 apositive signal is input to the ready to receive flip-flop 206, enablingthis flip-flop to switch when the ready to receive signal is present online 204. The negative signal from NOR gate 355 on line 236 is input tocounter 361, counter 234, and counter 238 lifting the reset to thesecounters. When the positive ready to receive signal arrives on line 204the ready to receive flip-flop 206, which has been enabled by reason ofits reset being lifted, is switched, providing a positive signal at itsQ terminal and a negative signal at its 6 terminal. The negative signalat the ready to receive flip-flop 6 terminal is inverted and fed on line217 to the start flip-flop 214, lifting the reset to the startflip-flop. The inverted ready to receive flip-flop signal on line 217 isalso fed to the counter 233, the parity flip-flop 351, and theflip-flops 240, 315-319, and 333 via line 231, lifting the reset forthese devices. Additionally, the inverted ready to receive flip-flopoutput on line 217 is fed via line 231 to the NAND gates 291-295,disabling these gates. The inverted ready to receive flip-flop output online 217 is also fed via a NOR gate 346 and an inverter 347 to thememory flip-flops 271-275, relieving the reset lines of each of theseflip-flops.

When the start mark 27 is sensed by the start ring scanning transducer98, a positive start signal (FIG. 1 lb) is received on line 203 andinput to NAND gate 211 which is enabled by the positive output of theready to receive flip-flop online 207. When the data mark 34 is sensedby the data mark scanning transducer 97, which occurs substantiallyconcurrently with the sensing of the start mark 27, a positive datasignal (FIG. 11c) is received online 202 and input to NAND gate 211,providing a negative signal (FlG. 11d) on line 212 to the input terminalP of the start flip-flop 214. This negative input at terminal P switchesthe start flip-flop 214, providing on flip-flop output line 216 apositive signal level to NAND gate 219, enabling this NAND gate. Sincethe start flip-flop 214 is only reset in response to a parity error,premature probe withdrawal, or a completed tag reading cycle, the NANDgate 219, once enabled, ordinarily remains enabled until the tag iscompletely read, gating all clock signals input thereto beginning withthe sensing the start mark 27 and continuing until the tag is completelyread.

The output of NAND gate 211 (FIG. 1111) is also fed via inverter 224 toNAND gate 223 to enable this NAND gate for the duration of the startsignal on line 203. With NAND gate 223 enabled for the duration of thestart signal, clock signals (P16. input on line 220 are gated (FIG. lle)to the counter 233 which provides on its output line 229 pulses with arepetition rate equal to one-half the clock pulse rate. The pulsesprovided by the counter 233 are input to a decade counter 234 whichaccumulates therein a count equal to onehalf the number of pulsesoccurring during the duration of the start signal present on line 203.The various output terminals A, B, C, 5 of the decade counter 234 areinput in various combinations to terminals 251-1 to 251-3, 252-1 to2524,...258 l to 258-4 of the NAND gates 251-258 of data samplingcircuit 230. For any given start and data signal width, one and one onlyof the NAND gates 251 258 is enabled by reason of the output of thedecade counter 234. In the illustrative example herein, it is assumedthat the data and start signal outputs from the data and starttransducers 97, 98 as a consequence of the sensing of data and startmarks 34 and 27 are six clock pulses wide. Accordingly, NAND gate 251has its four inputs 251-l to 251-4 maintained in a positive condition byreason of their being connected to outputs A, B, C, D of decade counter234, which are all positive by reason of the storage therein of a countof three corresponding to one-half the assumed width of the data andstart signals.

While the counters 233 and 234 are operating to store a count equal toone-half the clock pulses occurring during the start and data signalinterval, the clock pulses (FIG. 110) on line 220 are being gated (FIG.11]) via NAND gate 219 and an inverter 222 to the clock pulse decadecounter 238. The clock pulse decade counter 238 accumulates a count of10 clock pulses prior to recycling. The output of the clock pulse decadecounter 238 is input in various combinations to the NAND gates 251-258.Because of the constant recycling of the clock pulse decade counter 238,each of the NAND gates 251258 has its inputs 251- to 251-8, 252-5 to252-8, 258-5 to 258-8 simultaneously positive once every clock pulses.In the example given herein where the data aNd start signals are sixclock pulses wide, the NAND gate 251 has its terminals 251-1 to 251-4maintained continuously positive by decade counter 234. Since the sameNAND gate has its terminals 251-5 to 251-8 connected to the clock pulsedecade counter 238 in a manner such that these terminals areperiodically positive each time a count of three is accumulated indecade counter 238, the output (FIG. 11h) of the NAND gate 251 iscyclically positive on clock counts of 13, 23, 33, 43, 53,...Theseoutputs are provided from NAND gate 251 at a repetition rate twice thatrequired for sampling data. To utilize only alternate ones of theseoutputs, the output (FIG. 11:) of flip-flop 240 is gated, along with theoutput (FIG. 11h) of NAND gate 251 and the data signals (FIG. 110) online 2112, by sample NAND gate 260, providing on line 261 sample datasignals (FIG. l4j).

At clock counts of 18, 38, 58,...outputs (FIG. 113) are provided fromNAND gate 336 of the ring counter stepping circuit 320 to terminals CLof the ring counter flip-flops 315- 319 The first ring counter flip-flop315, which is primed by flip-flop 333, is stepped or set at the 18thclock count by the output from the ring counter stepping circuit 321) online 338. When the first ring counter flip-flop 315 is switched to itsset condition at the 18th clock count, the first memory stage flipflop271 is enabled via line 321.

Upon the occurrence of the 24th clock pulse, positive signals areprovided to the sample NAND gate 260 by the NAND gate 251 and theflip-flop 240, enabling the sample NAND gate, permitting it to gate toline 261 data signals present on line 202. In the illustrative examplegiven, reference being made to the character group 37 of FIG. 9 only, nodata mark (FIG. 110) is in the data position A of the first character37. Accordingly, no output is provided by sample NAND gate 260, that is,no negative pulse is provided on line 261, to the first memory flip-flop271. Hence, memory flip-flop 271 stores a logical 0."

As tag scanning continues, the 39th clock pulse causes the ring counterstepping circuit 320 to again provide a stepping signal (FIG. 11g) online 338 to all of the ring counter flipflops 315319. Since only thesecond ring counter flip-flop 316 is enabled, the stepping signaloccurring at the 38th clock count from the ring counter stepping circuit320 is effective to set only the second ring counter flip-flop 316. Withthe second ring counter flip-flop 316 set, an enable signal is providedto the second memory flip-flop 272 via line 322. At clock count 43,sample data NAND gate 260 is again enabled by the coincidence of outputsfrom NAND gate 251 (FIG. 11 and flipflop 214 (FIG. lli). Since in theexample under consideration, it is assumed a logical l is stored in thesecond data position 13 of the first character, a positive data signal(FIG. 11c.) on the data line 202 is fed to the sample gate 2611,providing a negative sample data signal (FIG. 111:) on line 261 to thememory flip-flops 271-275. Thus, the combination ofa logical l on thedata line 202, an output from NAND gate 251 at clock count 44, and anoutput from the flipflop 214 causes the data signal to be gated by NANDgate 260 to the memory flip-flops 271-275. Since only the second memoryflip-flop 272 is enabled by the ring counter 310, the signal gated byNAND gate 2611 switches only this flip-flop, storing a logical 1therein. With a logical "l" stored in flip-flop 272, a positive signallevel is output from this flip-flop on line 282 to a NAND gate 292 whichis enabled. NAND gate 292 provides a negative signal on its output line297.

At clock count 58, the ring counter 310 is stepped by the output (FIG.11g) on line 338 from the ring counter stepping circuit 320, setting thethird flip-flop 317 of this counter, the only ring counter flip-flopwhich is primed: with the third stage 317 of the ring counter 310 set,the third memory flipflop 273 is enabled via line 323. At count 63positive signals from NAND gate 251 (FIG. 11h) and flip-flop 214 (FIG.11:) are again concurrently input to NAND gate 260. Since no data mark(FIG. Me) is present in the third data position C of the first character37, no positive output data signal is provided on the data line 202(FIG. 11k) to the NAND gate 260, causing no negative sample data signalto be input to the memory flipflops 271-275. Consequently, a logical 0is stored in the enabled third flip-flop 273 of the memory.

Upon reaching a clock count of 78, a stepping signal (FIG. 11g) isprovided to the ring counter 310 by the stepping circuit 320 which stepsthe ring counter and sets the fourth ring counter flip-flop 318, thisflip-flop being the only one enabled at this time. When the fourth ringcounterflip-flop 318 is set, an input is provided to the fourth memorystage flip-flop 274 via line 324 enabling this memory stage flip-flop.At clock count 83, positive signals are again concurrently input to NANDgate 260 from NAND gate 251 (FIG. 11h) and flipflop 214 (FIG. 111'),enabling NAND gate 260. No data mark (FIG. is present in the fourth dataposition D of the first character, and consequently, a logical 0 ornegative signal is present on data line 202 and input to the NAND gate260, causing a positive output to be input to the memory flip-flops27ll275 from NAND gate 260. This positive output causes a logical O tobe stored in the memory flip-flop 274.

Upon occurrence of the 98th clock count, an output (FIG. Hg) is providedfrom the ring counter stepping circuit 320 which steps the ring countersetting the fifth position flip-flop 319, the only one primed. Settingof the fifth position flip-flop 319 of the ring counter 310 in turnenables the fifth memory flip-flop 275 via line 325. At clock count 103,positive signals are again input to the NAND gate 260 from NAND gate 251and flip-flop 214, enabling NAND gate 260. Since a logical l is presentin the fifth data position E of the first character, a positive signal(FIG. He) is input on line 202 to NAND gate 2611, producing a negativesignal (FIG. 11k) on line 261. This negative signal switches the fifthstage memory flip-flop 275, the only one enabled by the ring counter310, storing a logical l therein. With a logical l stored in memoryflip-flop 275, a positive signal is provided on the output line 285 ofthe flip-flop, in turn producing a negative signal on NAND gate outputline 3011.

Upon reaching a clock count of l 13, the character readout circuit 340provides an output (FIG. 111) to memory flip-flop reset terminals R,resetting those memory flip-flops 271275 which are in the set conditionby reason of having a logical i stored therein. When the memoryflip-flops 271275 are reset, the outputs of these memory flip-flopshaving a logical l stored therein change from positive to negative, inturn causing the outputs of their associated NAND gates 291295 to changefrom negative to positive. In the example herein, logical 1 sa arestored in flip-flops 272 and 275 Accordingly, only the flip-flops 272and 275 are reset by the output from the character readout circuit 3 10on line 276, and only NAND gates 292 and 295 have negative-to-positivesignal changes on their output lines 297 and 300. These latter signalchanges, when fed through inverters 302 and 305, constitute the outputof the memory 232 to the utilization device 205. The change in signallevel from negative to positive occurring on NAND gate output line 297occurring when the storage circuit 265 is read out, in addition to beingfed via inverter 302 to the utilization device 205, is also input to thecharacter counter 361, advancing this counter one count to reflect thefact that one character has been read from the tag.

The output of the character readout circuit 340 is also fed to theparity circuit 350 to sample the output of the parity error flip-flop351 to determine if a parity error has occurred. If no error hasoccurred, the output of the NAND gate 352 is positive. If a parity errorhas resulted, a negative output is provided by NAND gate 352 which isinput to NOR gate 355, providing a system reset signal on lines 236 and210.

The ring counter 310 is ready to recycle to successively enable thememory flip-flops 271-275 in response to successive stepping signals online 338 by reason of the 6 output terminal of the fifth ring counterflip-flop 319 being fed back to the first position ring counterflip-flop 315, priming the first position ring counter flip-flop.

The foregoing sequence of operations for reading the first character isrepeated 12 times until all l2 characters have been read, stored, andinput to the utilization device 205. When 12 characters of the tag havebeen read, stored, and input to the utilization device, a count of 12has been accumulated by the character counter 361, producing an outputfrom the character counter circuit 360. This output in combination withthe second start signal on line 203 and the enable signal of the fourthposition ring counter flip-flop 318 on line 324 causes NAND gate 370 toprovide a message complete signal. The message complete signal is inputto the indicator lamp flip-flop 381, setting this flip-flop and causingthe indicator lamp 17 to become illuminated. The message complete signalis also input to NOR gate 355, producing system reset signals on lines236 and 210, resetting the entire circuit 200. When the probe 12 isextended by reason of removal of the tag 14 from the read position 16,switch 165 opens, deenergizing driver circuit 199, and in turn scanmotor 103, scan lamp 183, and timing lamp 76. Additionally, a negativesignal is input to lamp flip-flop 381, resetting this flip-flop andextinguishing the indicating lamp 17.

LOGIC CIRCUIT EMBODIMENT 11 Structure The logic circuit 400 illustratedin FIGS. 13A and 138 includes the probe switch 165 connected betweenground and a probe flip-flop 401, which functions to provide arelatively negative input to the probe flip-flop 401 when the plunger 12is inserted into reader housing 10. The probe flip-flop 401 isresponsive to the state of the plunger switch 165 for controlling theenergization of the scanning motor 103, tag illumination lamp 17, andtiming lamp 76, and a ready to transmit flip-flop 402, to be described.The probe flip-flop 401, more specifically, includes a NAND gate 403having an input connected to a plunger or probe line 404 via an inverter405, an input connected to an end of message line 406, an inputconnected to a parity error line407, and an input connected from theoutput of a NAND gate 408. The NAND gate 408 is responsive to the outputof NAND gate 403 via line 411 and, via a differentiator 410, isresponsive to the plunger line 404.

Under nonread or normal conditions, the probe flip-flop 401 is in thereset condition providing a negative output from the NAN D gate 408, theprobe flip-flop having been placed in this condition by a negative endof message signal input thereto on line 406, or alternatively bynegative signals input thereto on lines 407 and 409 indicating,respectively, a parity error or a return of the probe to its normalextended position. When a tag is engaged with the probe and positionedat the read station urging the probe into its retracted position in thereader housing, the positive signal on probe line 404 becomes negative,providing on line 409 a positive signal to the NAND gate 403. Theoccurrence of the positive signal on line 409, along with the positivesignals normally present on the end of message line 406 and the parityerror line 407, causes the NAND gate 403 to produce a negative output onits output line 411 when the output of NAN D gate 408 becomes positivewhich occurs when the differentiated probe signal output fromdifferentiator 410 negatively pulses NAND gate 408. The negative outputfrom NAND gate 403 produces a positive output on line 412 from NAND gate408 which is coupled back to the input of the NAND gate 403 latching theprobe flip-flop 401 in its set state or condition.

The positive output on line 412, which occurs when the probe flip-flop401 is placed in its set condition by positioning a tag at the readstation, is input to a driver circuit 399, energizing this circuitwhich, in turn, energizes the scan motor 103, the illumination lamp 17,and the timing lamp 76.

The positive output on line 412 produced in response to positioning of atag at the read station is also input to the ready to transmit flip-flop402. The ready to transmit flip-flop 402 includes a NAND gate 416 havingone input responsive to line 412 and another input responsive to theoutput of NAND gate 417. NAND gate 417 has as its other input the outputof an inverter 418, inverter 418 in .turn having as its input the outputof a delay network 419 connected to respond to the output of the probeflip-flop on line 412. In the normal or nonread condition, the ready totransmit flip-flop 402 is in a reset condition by reason of a negativeinput signal on line 412 from the probe flip-flop 401, producing anegative output signal on line 420. In response to a positive signal onprobe flip-flop output line 412, the ready to transmit flipflop 402 isswitched to a set state, providing a positive signal on line 420. Thepositive signal on line 420 is connected to a utilization device 421,such as a buffer memory, cash register or the like.

The logic circuit 400 further includes a start circuit 423 including asits principle element a NAND gate 424 having its inputs connected to thedata line 425 via an inverter 426, the ready to receive line 427, andthe start line 428 via an inverter 429. The start circuit 423 provideson output line 430 from the NAND gate 424 a negative signal in responseto the simultaneous presence of a logical l data signal on data line 425manifested as a negative pulse, a positive signal on ready to receiveline 427 from the utilization device 421 indicating that the utilizationdevice is in a ready condition to receive information read from the tag,and a start signal on start line 428 manifested as a negative pulse. Thenegative signals on lines 428 and 425 occur simultaneously once perrevolution or scan of the ticket when the start and data ring scanningtransducers 98 and 97 aligned with the start and data rings are insensing relationship to the start mark 27 and the data mark 34 alignedtherewith.

The negative signal output from the start circuit 423 on line 430indicating the coincident receipt of a positive signal on the ready toreceive line 427 and negative signals on the data and start lines 425and 428, is input to a reset flip-flop 432, specifically is input to aNAND gate 433. The reset flip-flop 432, in addition to the NAND gate433, also includes a NAND gate 434, the output of which on line 435 isconnected to the other input of NAND gate 433. The NAND gate 434 has oneof its inputs connected to the output of NAND gate 433 and its otherinput connected to the output of the probe flip-flop 401 appearing online 412.

The reset flip-flop 432 in the normal nonread condition, is in theresetstate having been placed in this condition by the negative output fromthe probeflip-flop 401 appearing on line 412 which occurs when the probeflip-flop is reset by either a negative end of message signal on line406, a negative parity error signal on line 407, or a negative probesignal on line 409 representing the return of the probe to its normalextended position. With the reset flip-flop 432 in the reset condition,a negative signal is produced on output line 436. The reset signal online 436 resets an excess sample signal suppression

1. Apparatus for reading a tag having photosensible markreceivingpositions arranged in at least one circular pattern symmetricallyrelative to an aligner formed on the tag, said apparatus comprising: asupport, means mounted on said support and cooperable with said alignerfor properly locating a tag in a read position, sensing means mounted tosaid support in photosensing relationship to said circular pattern of atag located at said read position for sequentially photosensing themark-receiving positions of said pattern, clock signal generating meansfor generating clock signals at a rate substantially in excess of therate at which said markreceiving positions are sequentially photosensedby said sensing means, means responsive to said clock signals and to thesensing of a specified mark on said tag for generating an outputcorrelated to the width of said specified mark, and sampling meansresponsive to said width-correlated output and to said clock signals forgenerating sampling signals at intervals of clock signals and insynchronism with the sensing by said sensing means of the approximatemidpoint of said markreceiving positions.
 2. Apparatus for reading a taghaving photosensible mark-receiving positions arranged in at least onecircular pattern symmetrically relative to an aligner formed on the tag,said apparatus comprising: a support, means mounted on said support andcooperable with said aligner for properly locating a tag in a readposition, sensing means mounted to said support in photosensingrelationship to said circular pattern of a tag located at said readposition for sequentially photosensing the mark-receiving positions ofsaid pattern, clock signal generating means for generating clock signalsat a rate substantially in excess of the rate at which saidmark-receiving positions are sequentially photosensed by said sensingmeans, means for monitoring the width of a mark on said tag forgenerating an output correlated to said mark width, and sampling meansresponsive to said clock signals and to the sensing of a specified markon said tag for producing sampling signals at intervals of clock signalsand in synchronism with the sensing by said sensing means of theapproximate midpoint of said mark-receiving positions.
 3. Apparatus forreading a tag having photosensible mark-receiving positions arranged ina pattern, said apparatus comprising: a support, sEnsing means mountedto said support and movable in photosensing relationship to said patternof a tag for sequentially photosensing said mark-receiving positions ofsaid pattern, clock signal generating means for generating clock signalsat a rate substantially in excess of the rate at which saidmark-receiving positions are sequentially photosensed by said sensingmeans, means for monitoring the width of a mark on said tag forgenerating an output correlated to said mark width, and sampling meansresponsive to said clock signals and to the sensing of a specified markon said tag for producing sampling signals at intervals of clock signalsand in synchronism with the sensing by said sensing means of theapproximate midpoint of said mark-receiving positions.
 4. Apparatus forreading a tag having photosensible mark-receiving positions arranged inat least one circular pattern symmetrically relative to an alignerformed on the tag, said apparatus comprising: a support, means mountedon said support and cooperable with said aligner for properly locating atag in a read position, sensing means mounted to said support inphotosensing relationship to said circular pattern of a tag located atsaid read position for sequentially photosensing the mark-receivingpositions of said pattern, clock signal generating means for initiatinggeneration of, and generating, clock signals concurrently with theinitiation of photosensing, and photosensing, by said sensing means,said clock signal generating being at a rate substantially in excess ofthe rate at which said mark-receiving positions are sequentiallyphotosensed by said sensing means, sampling means for generatingsampling signals at intervals of clock signals and in synchronism withthe sensing by said sensing means of the approximate midpoint of saidmark-receiving positions, said sampling means including a. a firstcounter responsive only to clock signals generated during the sensing ofa specified mark for providing an output correlated with the width ofsaid mark, b. a second counter responsive to all clock signals generatedafter initiation of the sensing of said specified mark for periodicallyproviding at intervals of clock signals a plurality of outputscoincident with the approximate midpoints of different width marks, andc. means responsive to the outputs of said first and second counters forgenerating said sampling signals.
 5. The apparatus of claim 4 whereinsaid clock signal generating means and said sensing means concurrentlyinitiate clock signal generation and sequential mark positionphotosensing, respectively, and wherein said sampling means includesmeans for counting during the sensing of said specified mark on said tagonly alternate clock signals, and for thereafter counting all clocksignals to thereby generate said sampling signals.
 6. The method ofgenerating sampling signals in synchronism with the sequentialphotosensing of circularly arranged mark-receiving positions located ona tag, comprising the steps of: relatively moving said tag and ascanning transducer arranged in photosensing relationship to saidmark-receiving positions in a circular path to thereby sequentiallysense marks in said mark-receiving positions, generating clock signalsat a rate constituting a specified multiple of the rate at which saidmark-receiving positions are sequentially photosensed by said sensingmeans, counting clock signals generated during the sensing of saidspecified mark and, in response thereto, providing an output correlatedwith the width of said mark, counting all clock signals generated afterinitiation of the sensing of said specified mark and, in responsethereto, periodically providing, at intervals approximately equal tosaid specified multiple clock signals, a plurality of outputs coincidentwith the approximate midpoints of different width marks, and generating,in response to said counter outputs sampling signals at intervAls ofclock signals equal to said specified multiple and in synchronism withthe sensing by said sensing means of the approximate midpoint of saidmark-receiving positions.